1. Field of the Invention
The present invention relates in general to timing circuits, and more particularly to the use of a clock signal in combination with a phase-enable signal to provide multiple clock rates.
2. Description of Related Art
Electronic circuits often include discrete entities (functional units) that must be clocked at different rates. This is typically accomplished by providing a clock signal of a particular frequency and some conventional logic to divide the clock signal into one or more additional clock signals of varying rates.
Another conventional method of clocking different functional units at different rates is known as the "phase-enable" method. FIG. 1A illustrates a circuit 100 that makes use of a phase-enable signal to provide different clock rates to a functional unit A and a functional unit B. FIG. 1B is a waveform diagram illustrating the operation of circuit 100.
FIG. 1A includes a 66 MHz clock generator 105 that provides a 66 MHz clock on line CLK to functional unit A, functional unit B, and phase-enable logic 110. In response to the 66 MHz clock on line CLK, phase-enable logic 110 produces a phase-enable signal on a line PHASE.sub.-- EN to an enable node EN of unit B.
In the example of FIG. 1A, functional unit A is clocked on every rising edge of the 66 MHz clock on line CLK, as indicated by the letters "A" along the horizontal axis of the timing diagram of FIG. 1B. Functional unit B is also clocked on rising edges of the 66 MHz clock; however, in addition to a rising edge, unit B requires a logic one (e.g., 3.3 volts) on phase-enable line PHASE.sub.-- EN before unit B is clocked. Thus, unit B is only clocked when a rising edge of the 66 MHz clock on line CLK is coincident with a logic one phase-enable signal on line PHASE.sub.-- EN, as indicated by the letters "B" along the horizontal axis of the timing diagram of FIG. 1B. (Signals indicative of logic zeroes and logic ones, typically zero and 3.3 volts, respectively, are referred to herein as logic zeroes and logic ones for brevity.) Using the phase-enable method described above, even though a 66 MHz clock is provided to the clock inputs of both unit A and unit B, unit B is clocked at a 33 MHz rate. Of course, phase-enable logic 110 may be designed to provide a phase-enable signal more or less often to provide clocking frequencies of other than 33 MHz for unit B.
A problem associated with circuit 100 (and similar circuits) is that the phase of the phase-enable signal on line PHASE.sub.-- EN is not predictable. Assume, for example, that unit B includes an output buffer that is used to transmit data over an external 33 MHz bus. In such a case, the phase enable signal generated by phase-enable logic 110 must be synchronized with the 33 MHz bus clock. Unfortunately, circuit 100 provides no assurance of synchronization between the phase enable signal and the bus clock. That is, the rising edge of the phase-enabled clock signal of unit B may not be coincident with the rising edge of the external 33 MHz clock. There is therefore a need for a phase-enable and clock-generation circuit that provides timing of the appropriate phase and frequency for functional units operating at different frequencies.
While units A and B may each interface with devices that operate at different frequencies, some applications require that units A and B operate at the same frequency. It is therefore desirable to provide a timing circuit that selectively allows units A and B to operate either at the same or at different frequencies. Such a timing circuit would preferably allow units A and B to communicate with one another at the same clock frequency even when units A and B are clocked at different frequencies. Conventional phase-enable timing circuits do not offer such flexibility. There is therefore a need for a phase-enable and clock-generation circuit that supports different operational modes in which the functional units may be clocked at either the same or different clock frequencies.